Curricula Flowchart

curricula-flowchart

Introduction to VHDL (IHDL110)

Course Description

This one-day class is a general introduction to the VHDL language and its use in programmable logic design, covering constructs used in both the simulation and synthesis environments. By the end of this course, you will have a basic understanding of VHDL so that you can begin creating your own designs, using both behavioral and structural approaches. In the hands-on laboratory sessions, you will get to practice the knowledge you have gained by writing simple but practical designs.

At Course Completion

You will be able to:

  • Implement basic VHDL constructs,

  • Use VHDL design units: entity, architecture, configuration and package,

  • Create behavioral and structural models in VHDL,

Introduction to Verilog HDL (IHDL120)

Course Description

This class is a general introduction to the Verilog language and its use in programmable logic design, covering the basic constructs used in both the simulation and synthesis environments. By the end of this course, you will have a basic understanding of the Verilog module, data types, operators and assignment statements needed to begin creating your own designs, using both behavioral and structural approaches. In the hands-on laboratory sessions, you will get to practice the knowledge you have gained by writing simple but practical designs.

At Course Completion

You will be able to:

  • Create a basic Verilog module,

  • Understand the difference between simulation and synthesis environments,

  • Understand Verilog data types and operators and their uses,

  • Model hardware and test using behavioral and structural modeling constructs,

The Quartus Prime Software: Foundation (IDSW110)

Course Description

You will learn how to use the Quartus® Prime Pro Edition software to develop an FPGA design from initial design to device programming. You will create a new project, input new or existing design files, and compile your project. You’ll learn how to search for compilation information, use settings and assignments to adjust the results of compilation, and manage I/O-related assignments using the Pin Planner and the BluePrint Platform Designer. You will also learn about device programming files and how to program an FPGA device on your board. You will learn techniques to help you plan your design. You will employ Quartus Prime features that can help you achieve design goals faster. You will also learn how to plan and manage I/O assignments for your target device.

At Course Completion

You will be able to:

  • Make pre-project decisions to prepare for Quartus Prime design

  • Create, manage, and compile Quartus Prime projects

  • Use Quartus Prime tools to view the results of compilation

  • Review compilation results in various Quartus Prime software reports and graphical viewers

  • Plan and manage device I/O assignments using Pin Planner and the BluePrint Platform Designer

  • Understand device programming files and their use with the Quartus Prime Programmer

Introduction to the Qsys System Integration Tool (IQSYS101)

Course Description

This class will teach you how to quickly build designs for Intel® FPGAs using Intel’s Qsys system-level integration tool. You will become proficient with Qsys and expand your knowledge of the Quartus® II FPGA design software. You will learn how to quickly integrate IP and custom logic into a system. Since Qsys makes design reuse easy through standard interfaces, we will examine the Intel® FPGA Avalon-Memory Mapped and Streaming interfaces as well as introduce the AMBA™ AXI® interface standard from ARM®. The class provides a significant hands-on component, where you will gain exposure to tool usage as well as system and custom HDL component design.

At Course Completion

You will be able to:

  • Build digital systems in the Qsys tool

  • Integrate the files generated by Qsys into the Quartus II design flow

  • Create custom components with Avalon-MM and Avalon-ST interfaces and integrate them into your system

The Quartus II Software Debug and Analysis Tools (IDSW135)

Course Description

As FPGA designs become more complex, a larger part of development time is spent verifying designs. This course introduces the various debug tools included in the Quartus® II software and shows effective ways to debug an FPGA design, decreasing overall design development time. The class discusses various debugging tools: the SignalTap® II embedded logic analyzer (ELA), SignalProbe, In-System Sources & Probes, the Logic Analyzer Interface, System Console, Chip Planner and others. The focus is on the SignalTap II ELA, including hands-on lab exercises utilizing the tools on real designs.

At Course Completion

You will be able to:

  • Debug designs in-system using the SignalTap II embedded logic analyzer

  • Quickly route internal nodes to unused I/O pins without performing a full recompilation using SignalProbe incremental routing

  • View & edit embedded memory content using In-System Memory Content Editor

  • View results of compilation & make incremental design changes with Chip Planner

  • Connect internal debug nodes to an external logic analyzer using Logic Analyzer Interface

  • Debug a Qsys system using System Console

The Quartus Prime Software Design Series: Timing Analysis (IDSW120)

Course Description

You will learn how to constrain and analyze a design for timing using the TimeQuest timing analyzer in the Quartus® software. This includes understanding FPGA timing parameters, writing Synopsys Design Constraint (SDC) files, generating various timing reports in the TimeQuest timing analyzer & applying this knowledge to an FPGA design. Besides learning the basic requirements to ensure that your design meets timing, you will see how the TimeQuest timing analyzer makes it easy to create timing constraints to help you meet those requirements.

At Course Completion

You will be able to:

  • Understand the TimeQuest timing analyzer timing analysis design flow

  • Apply basic and complex timing constraints to an FPGA design

  • Analyze an FPGA design for timing using the TimeQuest timing analyzer

  • Write and manipulate SDC files for analysis and controlling the Quartus compilation

Design Optimization Using Quartus II Incremental Compilation (IDSW142)

Course Description

Debugging and optimizing a large FPGA design can be difficult and time consuming. Every change made to fix a problem or to help close timing requires the design to be completely recompiled. Not only can this take a long time, but the performance of untouched parts of the design can be affected. Integrating the work of different members on a team into a single design only adds to the complexity. In this class, you will learn how to use the incremental compilation feature and LogicLock regions in the Quartus® II software to help reduce compile times , preserve performance, and close timing. You’ll see how the tools in the Quartus II software make it easy to follow an incremental design flow that will help you finish your design cycles sooner.

At Course Completion

You will be able to:

  • Set up and perform incremental compilation through design partition creation and floorplanning in the Quartus II software

  • Understand the advantages and disadvantages of incremental compilation

  • Create good design partitions by following best practices

  • Lock performance of sub-designs by reusing previously compiled netlists

  • Close timing using incremental compilation

  • Apply incremental compilation to single-project and multi-project (team-based) design flows

Advanced VHDL Design Techniques (IHDL240)

Course Description

You will learn & practice efficient coding techniques for writing synthesizable VHDL for programmable logic devices (FPGAs & CPLDs). While the concepts presented will mainly target Intel® FPGA devices using the Quartus® II software, many can be applied to other devices & synthesis tools. You will gain experience writing behavioral & structural code & learn to effectively code common logic functions including registers, memory, & arithmetic functions. You will use VHDL constructs to parameterize your designs to increase their flexibility & reusability. You will also be introduced to testbenches, VHDL constructs used to build them, & common ways to write them. The exercises will use the Quartus II software to process VHDL code & ModelSim®-Altera software for simulation.

At Course Completion

You will be able to:

  • Develop coding styles for efficient synthesis when:

  • Targeting device features

  • Inferring logic functions

  • Using arithmetic operators

  • Writing state machines

  • Use Quartus II software RTL Viewer to verify correct synthesis results

  • Incorporate Intel structural blocks in VHDL designs

  • Write simple testbenches for verification

  • Create parameterized designs

Advanced Verilog HDL Design Techniques (IHDL230)

Course Description

You will learn efficient coding techniques for writing synthesizable Verilog for programmable logic devices (FPGAs and CPLDs). While the concepts presented mainly target Intel® FPGA devices using the Quartus® II software, many can be applied to other devices and synthesis tools as well. You will gain experience in behavioral and structural coding while learning how to effectively write common logic functions including registers, memory, and arithmetic functions. You will learn how to use Verilog constructs to parameterize your design, increasing their flexibility and reusability. You will be introduced to testbenches and Verilog constructs used when building them. The exercises will use the Quartus II software to synthesize Verilog code and the ModelSim®-Altera tool for simulation.

At Course Completion

You will be able to:

  • Implement synthesizable sequential and combinatorial RTL code

  • Design finite state machines using multiple encoding schemes

  • Develop simple testbenches for verification

  • Use tools in the Quartus II software to synthesize code and verify results

  • Run functional simulations in the ModelSim-Altera software

Advanced Qsys System Integration Tool Methodologies (IQSYS102)

Course Description

In this class, you will learn advanced features of Intel’s Qsys system level integration tool in the Quartus® Prime design software. You will learn how to simulate Qsys systems in ModelSim-Altera Edition using Avalon bus functional simulation models (BFMs), exercise, monitor, and debug systems with System Console, and build hierarchical Qsys systems. You will also learn how to further customize your components through Tcl scripting. Optimization techniques for improving performance and closing timing are also discussed. The class provides a significant hands-on component, where you will gain exposure to tool usage as well as system design.

At Course Completion

You will be able to:

  • Test custom components and entire systems with the Avalon Verification Suite in the ModelSim-Altera Edition simulation tool

  • Perform in-system control & debugging with System Console

  • Optimize systems to maximize performance and help close timing

  • Customize components using Tcl

  • Exploit Qsys’ hierarchical capability to add flexibility & scalability to your design

Timing Closure with the Quartus II Software (IDSW145)

Course Description

One of the greatest and most frustrating FPGA design challenges is closing timing. It is common to find, after performing a timing analysis on an FPGA design, that one or more timing reports show a timing failure. How can this be corrected? The answer is not always obvious. This class teaches techniques used by Design Specialists to close timing on designs that “push the envelope” of performance. Examples include thoroughly analyzing the design for timing failures, adjusting settings and assignments according to tool recommendations, selecting correct clock resources and writing HDL code for optimal performance. For Stratix 10, consider these courses instead: Performance Optimization with Stratix 10 HyperFlex Architecture, Advanced Optimization with Stratix 10 HyperFlex Architecture

At Course Completion

You will be able to:

  • Employ best practices for closing timing on an FPGA design in the Quartus II software

  • Analyze a TimeQuest-generated timing report as a starting point for timing closure

  • Use the tools available in the Quartus II software to help in meeting timing

  • Choose settings/assignments to get the best performance

  • Identify the most common types of timing failures and how to solve them

Advanced Timing Analysis with TimeQuest (IDSW125)

Course Description

Using the Quartus® II software and building upon your basic understanding of creating Synopsys Design Constraint (SDC) timing constraints, this class will guide you towards understanding, in more depth, timing exceptions. You will learn how to apply timing constraints to more advanced interfaces such as source synchronous single-data rate (SDR), double-data rate (DDR) and LVDS, as well as clock and data feedback systems. You will discover how to write timing constraints directly into an SDC file rather than using the GUI and then enhance the constraint file using TCL constructs. You will also perform timing analysis through the use of TCL scripts.

At Course Completion

You will be able to:

  • Write Tcl script files to automate constraining and analysis of FPGA designs

  • Apply timing exceptions to real design situations

  • Properly constrain and analyze the following design situations: source synchronous interfaces, external feedback designs, and high-speed interfaces containing dedicated SERDES hardware

Introduction to OpenCL for Intel FPGAs (IOPNCL110)

Course Description

OpenCL is a standard for writing parallel programs for heterogeneous systems. With the Intel FPGA SDK for OpenCL, OpenCL constructs are synthesized into custom logic for optimal acceleration on FPGA devices. This course introduces the basic concepts of parallel computing. It covers the constructs of the OpenCL standard & the Intel flow that automatically converts kernel C code into hardware that interacts with the host. In hands-on labs, you’ll write programs to run in emulation mode as well as on an FPGA board.

At Course Completion

You will be able to:

  • Describe high-level parallel computing concepts and challenges

  • Understand the advantages of using Intel's OpenCL solution

  • Know the basics of the OpenCL standard

  • Write simple programs in OpenCL

  • Compile, debug, and run OpenCL programs using the Intel SDK for OpenCL

Developing a Custom OpenCL BSP (IOPNCLBSP)

Course Description

The OpenCL model is based on heterogeneous accelerator devices and an FPGA is one of the most scalable & flexible devices available. Since an FPGA is not limited to the traditional host & accelerator communication interfaces, it also allows developers flexibility with ingress & egress of data. To leverage this flexibility requires building a custom Board Support Package for your custom board. We provide several reference platforms to get started that contain hardware & software layers that can be modified based on board requirements. This training will cover the steps to create a custom BSP compatible with the Intel SDK for OpenCL & you'll learn to generate hardware & software deliverables to convert the Arria® 10 reference platform BSP to an Arria 10 custom platform BSP.

At Course Completion

You will be able to:

  • Identify reference platform contents: Qsys IP components, script files, Quartus® files

  • Use the toolkit to generate a base design

  • Modify IP settings

  • Integrate custom components

  • Floorplan with LogicLock® Plus regions

  • Produce a timing closed base system

  • Program the FPGA using JTAG, flash or partial reconfiguration

  • Perform board diagnostics

  • Enable emulation

  • Implement an Intel SDK for OpenCL software layer to communicate with the accelerator board

Performance Optimization with Stratix 10 HyperFlex Architecture (IS10PERF)

Course Description

In the Performance Optimization with Stratix® 10 HyperFlex® Architecture course, you will learn Quartus® Prime software features and some basic design techniques that will enable your designs to take advantage of the Stratix 10 HyperFlex architecture. In the training, you will learn two steps to improving your performance with the HyperFlex architecture, namely Hyper-Retiming and Hyper-Pipelining, with each step allowing you to move your design up the performance curve. Note: While the focus of this course is the Stratix 10 device family, many of the techniques you will learn can be used to improve performance in other device architectures.

At Course Completion

You will be able to:

  • Describe the Stratix 10 device architecture, including the new HyperFlex architecture

  • Enable the Quartus software features that take advantage of the HyperFlex architecture

  • Evaluate possible design improvements using the Quartus software’s Fast Forward Compile feature

  • Improve your Stratix 10 design performance by understanding and enabling Hyper-Retiming

  • Improve your Stratix 10 design performance by implementing zero-latency Hyper-Pipelining

Building Gigabit Interfaces in 28-nm Devices (ITRNSCVR)

Course Description

In this course, you will learn how you can build high-speed, gigabit interfaces using the 28-nm embedded transceivers found in Cyclone® V, Arria® V and Stratix® V FPGA families. You will be introduced to the transceiver architecture and how the transceivers are configured to support various high-speed protocols. You will learn how to optimize and debug both the digital and analog sections of your transceiver design. You will gain an understanding of the transceiver reconfiguration controller and how you can use it to fine tune transceiver settings and add flexibility to your transceiver design. Lastly, you will be made aware of common “gotchas” that occur in transceiver designs and what steps you can take to avoid them. This course uses the Quartus® II software.

At Course Completion

You will be able to:

  • Implement high-speed serial protocols in Intel FPGA 28-nm embedded transceivers

  • Optimize analog settings to improve link behavior using Intel FPGA tools

  • Employ transceiver reconfiguration to dynamically change transceiver behavior in-system

  • Improve transceiver usage and avoid transceiver design issues by applying an understanding of device architecture to design situations

Building Interfaces with Arria 10 High-Speed Transceivers (ITRNSCVRGEN10)

Course Description

In this course, you will learn how you can build high-speed, gigabit interfaces using the 20-nm embedded transceivers found in Arria® 10 FPGA families. You will be introduced to the transceiver architecture and how the transceivers are configured to support various high-speed protocols. You will learn how to optimize and debug both the digital and analog sections of your transceiver design. You will gain an understanding of the transceiver reconfiguration interface that you can use dynamically adjust transceiver settings to add flexibility to your transceiver design. Lastly, you will learn how to create application and control logic that effectively manages Arria 10 transceiver resources.

At Course Completion

You will be able to:

  • Implement high-speed serial protocols in Arria® 20-nm embedded transceivers

  • Simulate transceiver operation using a generated simulation setup script file

  • Improve transceiver usage and avoid transceiver design issues by applying an understanding of device architecture to design situations

  • Optimize analog settings to improve link behavior using Intel FPGA tools

  • Employ transceiver reconfiguration to dynamically change transceiver behavior in-system

Creating PCI Express Links Using FPGAs (IPCIE)

Course Description

Are you beginning or working on a design that uses one or more PCI Express® interfaces? Do you have questions regarding bringing up your FPGA’s PCIe® link? Then this course should be of interest to you! We'll start with a high-level overview of the PCI Express protocol and from there you'll learn the design flow to target the Hard IP for PCI Express blocks found in Cyclone® V, Arria® V, Stratix® V and Arria 10 devices, particularly when using the Qsys system design tool. You'll see how to debug and test your PCIe links, both through simulation and in-system. You'll discover advanced device features to add more flexibility and capability to your PCI Express-based design. By the end of the day, you'll feel comfortable getting your own device’s PCIe link up and running.

At Course Completion

You will be able to:

  • Describe the features and functionality of the Hard IP for PCI Express block found in select Intel FPGA devices

  • Build a PCI Express solution targeting an FPGA using the Qsys system development tool

  • Generate a testbench to simulate the Hard IP for PCI Express and modify the testbench to perform custom tests

  • Debug a PCIe link using Intel FPGA debugging tools and transceiver features

Designing with an ARM-based SoC (ISOC101)

Course Description

Learn to design for a system containing the ARM® Cortex-A9 Hard Processor System (HPS) on Cyclone® V, Arria® V, & Arria 10 SoCs. This course focuses on the hardware aspects of designing the SoC system & includes hands-on labs to get you up & running quickly. Learn to add & configure the processor component into a Qsys system. You'll perform debug of the hardware system using standard debug tools such as SignalTap II logic analyzer & System Console. We'll discuss hardware to software files handoff that simplifies aspects of software development. You'll perform low-level debug of the FPGA interacting with the software debugger. We'll also discuss various ways the FPGA & HPS components can be loaded & booted. At completion, you'll be able to use the SoC device in your own design.

At Course Completion

You will be able to:

  • Create, manage, and compile an SoC based FPGA in the Qsys tool

  • Simulate the HPS interfaces using Qsys testbench and simulation model generation features

  • Bring up and debug an SoC with the System Console tool

  • Explain the hardware to software file handoff

  • Design and debug with a Cyclone V based development kit

Designing with the Nios II Processor (IEMB112)

Course Description

This course will leverage your knowledge of Qsys system design and teach you to embed a Nios® II 32-bit microprocessor soft core into your FPGA design. This course focuses on the hardware aspects of using the processor with hands-on labs that get you up and running quickly. Through lectures and exercises you will configure the processor component, learn how the software build flow is incorporated into the hardware flow, perform debug and bring up of a design, simulate your Nios II based design in ModelSim, and create custom instructions to perform hardware acceleration of software functions. At completion of the course, you will have the tools necessary to immediately start using the Nios II processor in your own designs or on a development kit and be productive right away.

At Course Completion

You will be able to:

  • Configure & compile a Nios II embedded processor design using Qsys & Quartus II software,

  • Create, compile, run, & debug embedded software projects for the Nios II processor using the Nios II Software Build Tools for Eclipse (SBTE),

  • Verify your FPGA design functionality with the System Console & the Nios II SBTE,

  • Simulate your Nios II-based system in ModelSim,

  • Use Qsys to incorporate custom instructions into an embedded Nios II system,

  • Design with a Nios II Development Kit

Advanced Optimization with Stratix 10 HyperFlex Architecture (IS10ADV)

Course Description

Are you targeting a Stratix® 10 device and want to learn how your design can reach the maximum core performance? In this course, you'll learn design techniques to enable you to unleash the full potential of the Stratix 10 HyperFlex architecture using Hyper-Optimization. You will learn how to identify logic structures that are limiting retiming and thus design performance. You will then learn how to modify your coding style and logic structures and, as a result, allow your design to achieve clock rates of up to 2 times compared to a non-optimized design, without changing overall design functionality. Note: While the focus of this course is the Stratix 10 device family, many techniques you will learn can be used to improve performance in other device architectures.

At Course Completion

You will be able to:

  • Learn to interpret complex retiming reports to locate & understand critical chains, design paths requiring further optimization for improved performance

  • Learn Hyper-Optimization techniques to restructure design logic to take advantage of the Stratix 10 HyperFlex architecture (or any FPGA architecture) using techniques such as 1) Unrolling loops, 2) Pre-computation to reduce loop size, 3) Shannon’s Decomposition, 4) Time-domain multiplexing retiming, 5) Hyper-Folding, and 6) Loop pipelining

Partial Reconfiguration with Intel FPGAs (IPR100)

Course Description

In this class, you will learn about the Partial Reconfiguration (PR) capabilities of Intel FPGAs. Starting in Intel 28 nm devices, you are able to change the functionality of a portion of an active FPGA, while the rest of the FPGA operates uninterruptedly. During this training, you will explore the benefits and limitations of PR, understand the design guidelines involving PR, and learn the steps necessary to enable this feature. During the exercises, you will prepare a design for PR using the Quartus® II software, complete the design of a PR controller, and test the feature on a development board.

At Course Completion

You will be able to:

  • Understand the Partial Reconfiguration design flow

  • Prepare a design for Partial Reconfiguration

  • Design and instantiate a Partial Reconfiguration controller

  • Create partial configuration files

  • Partially reconfigure a running FPGA design

  • Understand the limitations of Partial Reconfiguration

Designing with DSP Builder Advanced Blockset (IDSP220)

Course Description

Learn the timing-driven Simulink® design flow to implement high-speed DSP designs. This course focuses on implementing DSP algorithms using the advanced blockset capability of DSP Builder—an interface between Quartus® II software & MATLAB® and Simulink tools from The MathWorks. You'll analyze & design your DSP algorithm using the DSP Builder advanced blockset in MATLAB & Simulink. You'll explore architecture & performance tradeoffs with system-level constraints. Also you'll verify functionality & performance of generated hardware in the Quartus II software. Finally, you'll speed design time by incorporating ready made ModelIP cores in your design.

At Course Completion

You will be able to:

  • Implement DSP algorithms using Intel FPGA DSP Builder Advanced Blockset

  • Incorporate ModelIP and ModelPrim cores in a design

  • Explore design architecture and performance tradeoffs using system level constraints

  • Incorporate a DSP Builder Advanced Blockset model into a Qsys subsystem

  • Verify the hardware performance and implementation in Quartus II software

Developing Software for an ARM-based SoC (ISOC102)

Course Description

This course is for firmware and low-level software engineers and is intended to teach you about software bring-up and development on the embedded ARM® Cortex-A9 hard processor system (HPS) in an SoC. The course isn’t intended to teach you software application or driver development, but rather concentrates on the unique aspects of the embedded HPS software flow in an Intel SoC. You’ll learn everything needed to get started developing software for the HPS system, where to go for additional help, as well as how to use the Intel edition of the ARM DS-5 software development tool to debug your software.

At Course Completion

You will be able to:

  • Explain the hardware-to-software file handoff

  • Explain the stages in the HPS boot sequence & the boot scenarios

  • Create the second-state bootloader

  • Write bare-metal applications using Intel's Hardware Libraries

  • Get started with a variety of OSs for the ARM processor

  • Get support from the community portal on Linux development

  • Use DS-5 development studio to perform FPGA-adaptive software debug

Developing Software for the Nios II Processor (IEMB230)

Course Description

In this class, you will learn to develop and run embedded software for the Nios® II processor using the Nios II Embedded Development Suite. This course utilizes one of the Nios II Development Kits so that you can download, run, and debug your code on an Intel FPGA configured with a Nios processor. You will participate in discussions about the features and capabilities of the software tools. After taking this course, you should feel confident tackling your next embedded programming project.

At Course Completion

You will be able to:

  • Create software project from hardware deliverables

  • Manage software projects using the Nios II Software Build Tools for Eclipse

  • Download, run, & debug software on a board

  • Access Nios II peripherals from C

  • Create interrupt-driven C code

  • Reduce code size

  • Access custom instruction hardware from C

Optimizing OpenCL(IOPNCL210)

No class is being offered at this time